1. Technical Field
The present disclosure relates to a vertical power component capable of withstanding a high voltage (typically, greater than 500 V), and more specifically aims at the peripheral structure of such a component.
2. Discussion of the Related Art
FIG. 1 is a cross-section view of a vertical power component, illustrating a way of forming the periphery of a component in so-called “planar” technology to protect the component edges.
The component shown in this example is a triac comprising a lightly-doped N-type silicon substrate 1 (N−), with a doping currently ranging from 1014 to 1015 atoms/cm3, having its upper surface comprising a P-type doped well 3 (P) extending almost over the entire surface of the component, except at the periphery thereof, and having its lower surface comprising a P-type doped layer 5 (P) extending over the entire surface of the component. Upper well 3 contains a heavily-doped N-type region 4 (N+) and lower layer 5 contains a heavily-doped N-type region 6 (N+) in an area substantially complementary (in top view) to that occupied by region 4. Upper well 3 further contains a small heavily-doped N-type region 8 (N+). On the lower surface side of the component, a conduction electrode A2 coats the entire component surface, and on the upper surface side, a conduction electrode A1 coats region 4 and a portion of well 3, a gate electrode G coats region 8 and a portion of well 3, and an insulating layer 9, for example, made of silicon oxide, coats the portions of the upper surface which are not covered with electrodes. Whatever the biasing between electrodes A2 and A1, if a gate control is provided, the component becomes conductive. The conduction occurs from electrode A2 to electrode A1 through a vertical thyristor comprising regions 5, 1, 3, and 4, or from electrode A1 to electrode A2 through a vertical thyristor comprising regions 3, 1, 5, and 6. The thickness and the doping level of substrate 1 are calculated so that the triac, in the off state, can withstand high voltages, for example, voltages ranging between 600 and 800 volts.
The triac is fully surrounded with a P-type doped diffused wall 11 (P) formed from the lower and upper surfaces of the substrate and extending across the entire substrate thickness. On the lower surface side of the component, layer 5 laterally extends all the way to diffused wall 11 and, on the upper surface side, well 3 stops before diffused wall 11. Wall 11 especially has the function of insulating the lateral surfaces of substrate 1 and thus of avoiding possible short-circuits of the component due to solder rises when lower electrode A2 of the component is soldered to a contact area of an external device. To avoid the occurrence of breakdowns at the component edges, a distance should be provided between the limit of P-type well 3 and diffused wall 11. In this example, a heavily-doped N-type channel stop ring 13 (N+) is further arranged between well 3 and wall 11 and surrounds well 3.
A disadvantage of the structure of FIG. 1 has to do with the presence of a parasitic lateral bipolar transistor formed by P-type well 3 (emitter), N-type substrate 1 (base), and diffused P-type wall 11 (collector). Such a parasitic lateral transistor adversely affects the component performance in certain usage configurations. In particular, the presence of this transistor causes a decrease in the start sensitivity in quadrant Q4, that is, when a negative voltage is applied between electrodes A1 and A2 and when the component is started by application of a positive current on gate G. In other words, the presence of this transistor causes an increase in the intensity of the gate current necessary for a start in quadrant Q4. Further, the presence of the parasitic lateral transistor causes a decrease of the speed at which the component switches from the on state to the off state when the voltage between electrodes A1 and A2 switches from a positive value to a negative value.
To decrease the influence of the lateral parasitic transistor, it is known to provide a doping of the substrate with gold or with platinum, or an electron irradiation of the substrate, to decrease the lifetime of minority carriers in the base region of the PNP transistor, and thus decrease the transistor gain. Such a doping or such an irradiation however has the disadvantage of adversely affecting the conduction performance of the component (increase of the on-state voltage drop), of decreasing the component start sensitivity, and of increasing off-state leakage currents.